This invention relates to low dielectric constant layers for use in various applications. The invention also relates to methods of forming low dielectric constant layers having sufficient structural integrity to allow a wide range of VLSI fabrication operations.
As the features of microelectronic integrated circuits devices are reduced to smaller sizes, the electrical properties of the materials that constitute the devices will require change and improvement. One material that must be improved is the electrical insulator (“dielectric”) used between the wires, metal lines, and other elements of the circuit. Without improvement in the insulator material, there will be increased problems due to capacitive effects such as coupling (crosstalk) and propagation delay. The speed at which future circuits will operate will be limited by RC delay in the interconnect. These difficulties can be mitigated by preparing the circuit using an insulating material that possesses a dielectric constant as low as possible (a “low-k” dielectric layer).
Earlier technology nodes (i.e., the set of VLSI fabrication technologies associated with a particular critical dimension) employed dense materials such as silicon dioxide, silicon nitride, and cured silsesquioxanes as insulators. However, the dielectric constants of these materials range from 3.0–7.0. These values will be inadequate for future circuits. As yet the only fully dense (non-porous) materials with a dielectric constant less than about 2.4 are fluorinated polymers or fully aliphatic hydrocarbon polymers, but these have not met requirements for adhesion and thermal stability.
Thus, considerable effort has been directed towards the development of porous dielectric materials. These can be thought of as composite materials, with the value of their dielectric constants intermediate between that of air (dielectric constant of 1.0) and the fully dense phase. Several classes of dielectric films, including porous oxides, polymers, and porous polymers have been described in the art.
Nanoporous silica films are formed by a variety of techniques. In one example, a process deposits a monomeric precursor such as tetraethyl orthosilicate or TEOS (a siloxane) onto a substrate using a solvent, and then cross-links the precursors to form a continuous porous solid network. The resultant films are dried by direct solvent evaporation or treatment with supercritical fluids. The films are then subjected to a high-temperature annealing step. See for example, Changming et al., Materials Research Society Bulletin, vol. 22, no. 10, pp. 39–42 (1997).
Another technique involves developing inorganic-organic nanophase-separated hybrid polymer materials. These materials comprise organic polymers cast with silsesquioxane-based ladder-type polymeric structures. A casting solvent is used to dissolve the inorganic and organic polymer components. The materials are spin coated onto a substrate and upon application of high temperature, the hybrid phase-separated polymer materials are formed. See for example, Miller et al., Materials Research Society Bulletin, vol. 22, no. 10, pp. 44–48 (1997).
Certain problems arise in VLSI processing of partially fabricated devices having a porous dielectric material. A first problem arises because all porous dielectric materials for integrated circuit applications are “open cell” dielectrics. In other words, the individual pores contact and open into one another. Consequently, the pores of these materials provide long paths throughout the interior of the dielectric material. Gases and liquids contacting the outer surfaces of open cell dielectric materials can thereby penetrate deep into the layer's interior. This gives rise to a particularly difficult problem during conformal depositions of conductive barrier layers or seed layers. Precursor gases or plasma for these processes can penetrate deep into the open cell matrix of the dielectric layer. There they deposit and get converted to the conductive barrier layer or seed layer. This renders large portions of the dielectric layer unacceptably conductive. Examples of extremely conformal deposition processes where the problem is most pronounced include certain forms of chemical vapor deposition (CVD) and atomic layer deposition (ALD). Note that less conformal processes such as physical vapor deposition (PVD) do not deposit conductive material within the pore network, but they do a poor job of covering the discontinuous porous side-walls of a trench or via.
Another problem arises because porous materials lack the mechanical strength of non-porous materials. As a consequence, when a planarization technique such as chemical mechanical polishing (CMP) is employed to remove excess copper or other material, the pressure applied to the wafer during that process can crack or crush the underlying dielectric material.
The current porous materials and associated processing techniques have failed to meet the demands of next generation VSLI fabrication. Obviously, the problems will only get worse as technologies move to ever smaller feature dimensions. Improved materials and processing are required.